Modern integrated circuits contain millions of individual elements that are formed by patterning the materials, such as silicon, metal and/or dielectric layers. A set of processing steps is performed on a lot of semiconductor wafers to from the elements. For example, in lithography process, a process layer is formed on a semiconductor wafer, and a photoresist pattern then formed on the process layer by performing known photolithography techniques. Next, a trimming process is performed on the process layer by the photoresist pattern as a mask. As such, an element like a gate electrode of a transistor is obtained.
Critical dimensions (CDs), in either geometry or spacing, are used to monitor the pattern, and to ensure those to meet designed values of a customer specification. CD bias refers to an extent that the designed values mismatch actual values. Ideally, CD bias approaches zero, but in actuality, CD bias exist and affect performance and operation of a resulted semiconductor device, so as the wafer yield. Therefore, controlling of CD bias is needed.